With conventional photolithographic processing techniques, integrated circuits are created on a semiconductor wafer by exposing photosensitive materials on the wafer through a mask or reticle. The wafer is then chemically and mechanically processed to build up the integrated circuit or other device on a layer-by-layer basis.
As the components of the integrated circuit or other device to be created become ever smaller, optical distortions occur whereby a pattern of features defined on a mask or reticle do not match those that are printed on the wafer. As a result, numerous resolution enhancement techniques (RETs) have been developed that seek to compensate for the expected optical distortions so that the pattern printed on a wafer will more closely match the desired layout pattern. Typically, the resolution enhancement techniques include the addition of one or more subresolution features to the mask pattern or creating features with different types of mask features such as phase shifters. Another resolution enhancement technique is optical and process correction (OPC), which analyzes a mask pattern and moves the edges of the mask features inwardly or outwardly or adds features such as serifs, hammerheads, etc., to the mask pattern to compensate for expected optical distortions.
While RETs improve the fidelity of a pattern created on a wafer, further improvements can be made.